Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

Design and Feasibility of Multi-Gb/s Quasi-Serial Vertical Interconnects based on TSVs for 3D ICs

This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced by serialized links to save silicon area and increase yield. Detailed analysis conducted in 90 nm CMOS technology shows that the proposed 2-Gb/s/pin quasi-serial link requires approximately five times less area than its parallel bus equivalent at same data rate for a TSV diameter of 20 um

Surface-Tension-Driven Multi-Chip Self-Alignment Techniques for Heterogeneous 3D Integration

Surface-tension-driven self-alignment (SA) is a promising technique for heterogeneous die-level stacking. Multiple dies can be manipulated in parallel at minimal cost. A defined amount of water present between the die and a carrier substrate is used to align the components. The minimization of the water-air interface is the driving force. Most studies were performed with a completely wetted chip surface with a resulting alignment of die periphery to carrier. This achieves a maximal die-pad to carrier-pad alignment quality equal to the dicing accuracy, which is typically +/- 25 mu m. To further improve the pad-to-pad alignment accuracy, we propose a pad-assisted SA technique. With an initial placement quality of less than half a pad pitch, this technique achieves submicron SA accuracy. Furthermore, we extend the process to dies with Au studs needed in later thermo-compression bonding. Design rules to design a stable process are reported. A meniscus minimization model is built, which explains the experimental results and helps to design new SA patterns

A two-level hierarchical discrete-device control method for power networks with integrated wind farms

Abstract Power systems depend on discrete devices, such as shunt capacitors/reactors and on-load tap changers, for their long-term reliability. In transmission systems that contain large wind farms, we must take into account the uncertainties in wind power generation when deciding when to operate these devices. In this paper, we describe a method to schedule the operation of these devices over the course of the following day. These schedules are designed to minimize wind-power generation curtailment, bus voltage violations, and dynamic reactive-power deviations, even under the worst possible conditions. Daily voltage-control decisions are initiated every 15 min using a dynamic optimization algorithm that predicts the state of the system over the next 4-hour period. For this, forecasts updated in real-time are employed, because they are more precise than forecasts for the day ahead. Day-ahead schedules are calculated using a two-stage robust mixed-integer optimization algorithm. The proposed control strategies were tested on a Chinese power network with wind power sources; the control performance was also validated numerically

Mechanical Analysis of the Failure Characteristics of Stope Floor Induced by Mining and Confined Aquifer

Mining above confined aquifer has become an important task for water inrush prevention in China. To study the failure characteristics of stope floor along the strike, a mechanical model under combined action of mining and confined aquifer was constructed, and the distribution of vertical stress, horizontal stress, and shear stress was obtained. Based on the Mohr–Coulomb criterion, the failure range of the floor is determined and verified by the in situ test. The results indicate the following. (1) Both vertical stress and horizontal stress in the stope floor take the junction of stress increasing area and stress decreasing area as the dividing line, forming two groups of “convex arches” at the solid coal side and the goaf side, respectively. (2) The vertical stress gradient in the solid coal side is significantly higher than that in the goaf side, while the horizontal stress gradient in the solid coal side is similar to that in the goaf side. The shear stress distribution is divided into three regions by the boundary between positive and negative shear stress, which makes the stope floor in this area to show compression shear or tension shear failure. (3) According to the in situ test, the maximum floor failure depth of 41503 working face is 11.38 m, which is quite close to the theoretical calculation result of 9.68 m. (4) Applying the mechanical model to five other coal mines with different mining conditions and stress states, the maximum absolute error between the measured and theoretical values of floor failure depth is 1.1 m, the average absolute error is 0.8 m, the maximum relative error is 8.2%, and the average relative error is 6.5%. The study provides a certain mechanical basis and reference for the floor failure mechanism induced by mining and confined aquifer

Performance and Mechanism of Nanoporous Ni@NiO Composites for RhB Ultrahigh Electro-Catalytic Degradation

Today, the development of new self-supporting electrode materials with high porosity and excellent degradation properties is of great importance for the removal of dye pollutants. Herein, this work synthesized nanoporous nickel@nickel oxide (np-Ni@NiO) electrode containing an amorphous alloy in the middle interlayer. The nanoporous structure endowed the electrode with more active sites and facilitated the ion/electron transport. The electrochemical active surface area was about 185.5 cm2. The electrochemical degradation of rhodamine B (RhB) using a np-Ni@NiO electrode was systematically investigated. The effects of technology paraments (NaCl concentration, the applied potential and pH) on electro-catalytic degradation were explored. An RhB removal rate of 99.68% was achieved in 30 s at optimized conditions, which was attributed to the unique bicontinuous ligament/pore structure and more active sites on the surface, as well as lower charge transfer resistance. In addition, the degradation mechanism of RhB in electrochemical oxidation was proposed, according to active species capture tests and EPR measurements